// Test file for connect command with feedthrough modules
// This tests the -v (verbose) flag showing wire names between modules

module top (
    input wire clk,
    input wire rst_n,
    input wire [31:0] data_in,
    output wire [31:0] data_out,
    output wire valid
);

    // Internal wires connecting modules
    wire [31:0] wire_a_to_fd1;
    wire [31:0] wire_fd1_to_fd2;
    wire [31:0] wire_fd2_to_b;
    wire valid_a_to_fd1;
    wire valid_fd1_to_fd2;
    wire valid_fd2_to_b;

    // Source module
    module_a u_module_a (
        .clk(clk),
        .rst_n(rst_n),
        .data_in(data_in),
        .data_out(wire_a_to_fd1),
        .valid_out(valid_a_to_fd1)
    );

    // First feedthrough module
    feedthrough_1 u_fd1 (
        .clk(clk),
        .rst_n(rst_n),
        .data_in(wire_a_to_fd1),
        .data_out(wire_fd1_to_fd2),
        .valid_in(valid_a_to_fd1),
        .valid_out(valid_fd1_to_fd2)
    );

    // Second feedthrough module
    feedthrough_2 u_fd2 (
        .clk(clk),
        .rst_n(rst_n),
        .data_in(wire_fd1_to_fd2),
        .data_out(wire_fd2_to_b),
        .valid_in(valid_fd1_to_fd2),
        .valid_out(valid_fd2_to_b)
    );

    // Destination module
    module_b u_module_b (
        .clk(clk),
        .rst_n(rst_n),
        .data_in(wire_fd2_to_b),
        .data_out(data_out),
        .valid_in(valid_fd2_to_b),
        .valid_out(valid)
    );

endmodule

// Source module definition
module module_a (
    input wire clk,
    input wire rst_n,
    input wire [31:0] data_in,
    output reg [31:0] data_out,
    output reg valid_out
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            data_out <= 32'h0;
            valid_out <= 1'b0;
        end else begin
            data_out <= data_in;
            valid_out <= 1'b1;
        end
    end
endmodule

// First feedthrough module
module feedthrough_1 (
    input wire clk,
    input wire rst_n,
    input wire [31:0] data_in,
    output reg [31:0] data_out,
    input wire valid_in,
    output reg valid_out
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            data_out <= 32'h0;
            valid_out <= 1'b0;
        end else begin
            data_out <= data_in;
            valid_out <= valid_in;
        end
    end
endmodule

// Second feedthrough module
module feedthrough_2 (
    input wire clk,
    input wire rst_n,
    input wire [31:0] data_in,
    output reg [31:0] data_out,
    input wire valid_in,
    output reg valid_out
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            data_out <= 32'h0;
            valid_out <= 1'b0;
        end else begin
            data_out <= data_in;
            valid_out <= valid_in;
        end
    end
endmodule

// Destination module definition
module module_b (
    input wire clk,
    input wire rst_n,
    input wire [31:0] data_in,
    output reg [31:0] data_out,
    input wire valid_in,
    output reg valid_out
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            data_out <= 32'h0;
            valid_out <= 1'b0;
        end else begin
            data_out <= data_in;
            valid_out <= valid_in;
        end
    end
endmodule
